Within an integrated circuit, it is known to employ adaptive power management or dynamic voltage scaling (DVS) techniques in order to reduce the power dissipation on a chip. Adaptive power management is becoming ever more important as process geometries decrease. In particular, with leading edge nanometer technology, the individual components are becoming significantly smaller in size, and the decrease in size is giving rise to a significant increase in power consumption due to leakage current, leakage current being the current that is drawn by a component when it is in theory turned off.
As circuits become smaller and smaller due to technology scaling, the supply voltage to those circuits has to be reduced to reduce dynamic power consumption. However, a side effect of such scaling is that the threshold voltage and channel length of the transistors need to be lowered to prevent speed degradation, and this lowering of the threshold voltage makes the transistors more leaky, i.e. the leakage current increases as the threshold voltage decreases. For example, for each 100 mV reduction in threshold voltage, the sub-threshold leakage current (for a MOSFET transistor this being the leakage current between the source and drain of the transistor) can increase by a factor of ten to a hundred.
One common mechanism used in adaptive power management techniques in order to save energy is to shut down blocks of components on a chip when those blocks of components are not performing any useful function, for example when they are waiting for instructions from other parts of the system. Such blocks of components can be shut down using power gating techniques, where power gating circuitry is placed between a source voltage supply and the block of components, and when it is desired to shut the block of components down, the power gating circuitry isolates the block of components from the source voltage supply.
However, whilst such power gating techniques have traditionally given rise to significant energy savings, the ability for such power gating techniques to achieve significant energy savings is being compromised in integrated circuits based on leading edge nanometer technology, due to the reduced size of the components, and the associated increase in leakage current. For example, power gating circuitry is usually constructed using transistors such as PMOS transistors, and as a transistor's size decreases, its channel length is reduced, and this increases its channel leakage current. Accordingly, it is found that when the transistors in the power gating circuitry are turned off in order to isolate the block of components from the source voltage supply, those transistors are in fact not fully turned off, and significant leakage current through them can occur. This in turn results in the block of components itself not being fully powered down, and accordingly further leakage current being drawn by those components.
One known way to seek to address this problem is to force the power switch transistors of the power gating circuitry into a super cut-off region. For example, considering power gating circuitry formed of PMOS transistors, the voltage on the gate of the PMOS transistors can be driven to a voltage level above the source voltage supply level provided between the source and drain of the transistor. Such a mechanism can significantly reduce leakage current. However, blocks of components may be power gated for significant amounts of time, which means that such power gating transistors are exposed to a gate voltage that exceeds the source voltage supply for significant periods of time. This is undesirable, as such increased gate voltages serve to reduce the operational life (increase “wear out”) of the transistors by slowly increasing their threshold voltage. Accordingly, whilst it is desirable to drive the power gating transistors into a super cut-off region in order to reduce leakage current, this has to be balanced against the desired life expectancy for the circuit which is reduced by the driving of such power gating transistors into the super cut-off region.
The article “Gate Bias Circuit for an SCCMOS Power Switch Achieving Maximum Leakage Reduction” by A Valentian et al, IEEE 2007 describes a technique for determining an optimal voltage to be applied to the gate of a power switch transistor in order to maximise leakage gain, dependent on operating conditions. The paper describes a circuit that uses two identical devices configured to measure the sub-threshold current and the gate leakage current. A charge pump is driven to vary the gate voltage dependent on a comparison between the sub-threshold current and the gate leakage current.
The article “A Super Cut-Off CMOS (SCCMOS) Scheme for 0.5V Supply Voltage with Picoampere Standby Current” by H Kawaguchi et al, IEEE Journal of Solid-State Circuits, Volume 35, No. 10, October 2000, Pages 1498 to 1501, describes a technique for using a four-stage charge pump to overdrive the gate of a low threshold voltage PMOS power gate switch transistor by a voltage that is 400 mV higher than the source voltage supply.
The article “Techniques for Aggressive Supply Voltage Scaling and Efficient Regulation” by A Dancy et al, IEEE 1997 Custom Integrated Circuits Conference, Pages 579 to 586, describes a leakage mitigation technique that uses a triple-well CMOS process to provide substrate voltage control. The logic circuits to be power gated are implemented using low threshold devices and are gated using series connected high threshold switches.
The article “Standby Power Management for a 0.18 μm Microprocessor” by L Clark et al, ISLPED '02 Aug. 12 to 14, 2002, Monterey, Calif., USA, Pages 7 to 12, describes a technique to mitigate leakage current using a back-bias scheme.
It would be desirable to provide an improved technique for controlling power gating in an integrated circuit, which enables the leakage current to be controlled whilst also seeking to reduce the impact on wear out of the integrated circuit.